Integrated circuit technology relies on transistors to formulate functional circuits. The complexity of these circuits requires the use of an ever-increasing number of transistors. During the manufacture of some integrated circuits, field effect transistor (FET) gate electrodes and gate electrode interconnects are etched from an electrically conductive layer that covers other circuitry. For example, in semiconductor memory circuits, wherever a word line passes over a field oxide region, it functions as a gate electrode interconnect; wherever the word line passes over a gate dielectric layer overlying an active region, the word line functions as a gate electrode.
In previous integrated circuits, gate electrodes and electrode interconnects were often etched from a doped polycrystalline silicon (polysilicon) layer. However, faster operational speeds and low gate stack heights that are desirable for some applications could not be obtained using the polysilicon layer. Faster operational speeds, for example, are required for certain high-speed processor and memory circuits. Reduced gate stack heights are desirable for increasing the planarity of the integrated circuit to obtain better photolithographic resolution that is required with miniaturization. To achieve increased operational speeds and lower gate stack heights in more recent integrated circuits, it became necessary to reduce the sheet resistance of the conductive layer from which the gates and gate interconnects were formed.
As semiconductor devices continued to scale to smaller dimensions, reduced resistance in the gate electrode lines of FETs also became more important. One way to reduce the resistance and the topology in a gate electrode was to use a combination of polysilicon and refractory metal films. These are known as polycide gates.
One challenge in dynamic random access memory (DRAM) technology is to get the memory cell to hold a charge for longer periods of time. A longer period of time requires less frequent refreshing of the memory cell and allows for more efficient use of the memory controller for read/write/refresh demands. Leakage from the memory cell is a function of many things. There are several leakage mechanisms and pathways. For example, increased temperature will increase leakage. Impurities, traps, and defects in the junction or in the depletion width of the junction represent other leakage pathways. Further, impurities etc. in the source and drain, and defects in or near the gate will also increase leakage. Another cause of leakage includes gate-induced drain leakage (GIDL), also referred to as band-to-band tunneling. Another cause of leakage include sub-threshold leakage, which is backward tunneling of charge from the source to the drain. Another source of leakage is through the dielectric into the polysilicon, referred to as gate leakage.
Three oxidation-promoting processes are used during the gate fabrication that may cause a significant amount of metal to oxidize and to volatilize and redeposit in the substrate junctions and other regions. This redeposition of metal impurities is one source for many leakage pathways. The first is a chemical vapor deposition (CVD) of silicon dioxide or silicon nitride dielectric material over the metal layer prior to the gate stack etch. This dielectric material may become the dielectric cap for the gate stack.
The second oxidation-promoting process is a light thermal reoxidation. Various processes are used. They are sometimes referred to as a gate thickening oxidation (GTO), sometimes referred to as a “poly smile” oxidation, and sometimes referred to as “selective steam”. The light thermal reoxidation process is carried out to oxidize some of the polysilicon in the gate stack without causing the volumetric expansion of the metal in the gate stack by resisting the formation of a metal oxide.
In the selective steam exemplary process, a wet hydrogen oxidation procedure was developed to allow the silicon to oxidize while leaving the metal such as tungsten unaffected in a post gate etch oxidation. The method was based on thermodynamic calculations which showed that at, for example, 1000E C and a P(H2O)/P(H2) ratio (partial pressure ratio of H20 and H2) of about 1.0×10−05, the equilibrium:Si+2H2O<====>SiO2+2H2 tends toward oxidation of Si, andW+3H2O<====>WO3+3H3 tends toward reduction of WO3 to W. Therefore, it was possible to oxidize silicon again such that the oxidation rate of W would be reduced. However, W may volatilize during processing and recombine with the substrate in a manner that poisons active areas.
The third oxidation-promoting process is a sidewall formation of a dielectric that becomes the gate spacer.
During oxidation-promoting processes, the oxidation of silicon, including polysilicon, is self limiting to a degree. In other words, only a portion of the silicon will oxidize. Metals such as tungsten, are less self limiting. Accordingly, the tungsten may oxidize to a significant amount and even vaporize during any of these oxidation-promoting processes. Further, some metal may volatilize and recombine with portions of the semiconductor in ways that are detrimental to both device yield and field use life.